1. Field of the Invention
The present invention relates generally to microelectronic conductor structures, as employed within microelectronic fabrications. More particularly, the present invention relates to low dielectric constant microelectronic conductor structures with enhanced adhesion and attenuated electrical leakage, as employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. For reference purposes, comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications are intended as dielectric materials typically having dielectric constants in a range of from about 2.0 to about 4.0. For comparison purposes, conventional dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications, such as but not limited to conventional silicon oxide dielectric materials, conventional silicon nitride materials and conventional silicon oxynitride materials as employed for forming microelectronic dielectric layers within microelectronic fabrication, typically have dielectric constants in a range of from about 4.0 to about 8.0.
Comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications may include, but are not limited to, spin-on-polymer (SOP) dielectric materials, spin-on-glass (SOG) dielectric materials, amorphous carbon dielectric materials, fluorosilicate glass (FSG) dielectric materials and aerogel (i.e., air or insulating gas entrained) dielectric materials. As is understood by a person skilled in the art, comparatively low dielectric constant dielectric materials are desirable within the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as within such applications comparatively low dielectric constant dielectric materials provide microelectronic fabrications with enhanced microelectronic fabrication speed, reduced patterned microelectronic conductor layer parasitic capacitance and reduced patterned microelectronic conductor layer cross-talk.
While comparatively low dielectric constant dielectric materials are thus desirable in the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications, comparatively low dielectric constant dielectric constant dielectric materials are nonetheless not entirely without problems within microelectronic fabrications when employed for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications. In that regard, and in particular with respect to damascene methods for forming within microelectronic fabrications microelectronic conductor structures comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, there is often observed within such microelectronic conductor structures decreased adhesion and enhanced electrical leakage.
It is thus desirable in the art of microelectronic fabrication to provide microelectronic conductor structures, and methods for fabrication thereof, comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with enhanced adhesion and attenuated electrical leakage.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic conductor structures, and in particular microelectronic conductor structures comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with desirable properties in the art of microelectronic fabrication.
For example, Zhao et al., in U.S. Pat. No. 6,100,184, discloses a method for efficiently forming within a microelectronic fabrication a microelectronic conductor structure comprising a patterned microelectronic conductor stud layer contacting a patterned microelectronic conductor interconnect layer, wherein each of the patterned microelectronic conductor stud layer and the patterned microelectronic interconnect layer has formed adjacent thereto a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material. In order to realize the foregoing object, the method comprises a dual damascene method which employs: (1) a pair of patterned first microelectronic dielectric layers formed of a first comparatively low dielectric constant dielectric material which defines a via, having formed thereover; (2) a pair of patterned second microelectronic dielectric layers formed of a second low dielectric constant dielectric material which defines a trench contiguous with the via, and further wherein the patterned microelectronic conductor stud layer which contacts the patterned microelectronic conductor interconnect layer is formed within the via contiguous with the trench while employing a single chemical mechanical polish (CMP) planarizing method.
In addition, Zhao, in U.S. Pat. No. 6,071,809, discloses a related dual damascene method for forming within a microelectronic fabrication a microelectronic conductor structure comprising a patterned microelectronic conductor stud layer contiguous with a patterned microelectronic conductor interconnect layer, each having formed adjacent thereto a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material, in part absent delamination within the microelectronic conductor structure. To realize the foregoing object, the dual damascene method employs when forming within the microelectronic conductor structure while employing a single chemical mechanical polish (CMP) planarizing method the patterned microelectronic conductor stud layer contiguous with the patterned microelectronic conductor interconnect layer a composite hard mask layer/polish stop layer comprising a silicon nitride polish stop material layer having formed thereupon a silicon oxide hard mask material layer.
Desirable in the art of microelectronic fabrication are additional methods through which there may be formed within microelectronic fabrications microelectronic conductor structures comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of low dielectric constant dielectric materials, with enhanced adhesion and attenuated electrical leakage.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a microelectronic conductor structure and a method for forming the microelectronic conductor structure.
A second object of the present invention is to provide a microelectronic conductor structure and a method for forming the microelectronic conductor structure in accord with the first object of the present invention, wherein the microelectronic conductor structure is formed with enhanced adhesion and attenuated electrical leakage.
A third object of the present invention is to provide a microelectronic conductor structure and a method for forming microelectronic conductor structure in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a microelectronic conductor structure and a method for forming the microelectronic conductor structure.
In accord with the objects of the present invention, the microelectronic conductor structure of the present invention in a first instance comprises a substrate. The microelectronic conductor structure of the present invention also comprises formed over the substrate a silicon carbide layer. The microelectronic conductor structure of the present invention further also comprises formed upon the silicon carbide layer a silicon nitride layer. The microelectronic conductor structure of the present invention still further also comprises formed upon the silicon nitride layer a patterned low dielectric constant dielectric layer. Finally, the microelectronic conductor structure in accord with the present invention yet still further also comprises formed interposed between the patterns of the patterned low dielectric constant dielectric layer a patterned conductor layer.
The microelectronic conductor structure in accord with the present invention contemplates at least one method for forming the microelectronic conductor structure in accord with the present invention.
The present invention provides a microelectronic conductor structure and a method for forming the microelectronic conductor structure, wherein the microelectronic conductor structure comprises a patterned microelectronic conductor layer having interposed between its patterns a dielectric layer formed of a low dielectric constant dielectric material, where the microelectronic conductor structure is formed with enhanced adhesion and attenuated electrical leakage.
The present invention realizes the foregoing objects by employing when forming the microelectronic conductor structure in accord with the present invention, and formed over a substrate, a silicon carbide layer, in turn having formed thereupon a silicon nitride layer, in turn having formed thereupon a patterned low dielectric constant dielectric layer, finally in turn having formed interposed between its patterns a patterned conductor layer.
The method of the present invention is readily commercially implemented.
As will be illustrated in greater detail within the context of the Description of the Preferred Embodiment, as set forth below, the present invention employs methods and materials as are generally known in the art of microelectronic fabrication, but employed within the context of a specific process ordering to provide: (1) a microelectronic conductor structure in accord with the present invention; and (2) a method for forming a microelectronic conductor structure in accord with the present invention. Since it is thus a specific process ordering of methods and materials which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.